CMOS technology is well known in the art. CMOS technology has become the dominant technology for information processing because of its low operating voltage, low power consumption, and short channel length with accompanying high speed. Usually, other metal-oxide field effect transistor (MOSFET) technologies utilize only n-channel depletion-type or enhancement-type transistors summarized by the name NMOSFET, or PMOSFET technology which employs transistors with p-channels. However, CMOS technology is complementary because both n-channel and p-channel transistors are integrated on one chip.
A CMOS inverter circuit serves as a fundamental building block in CMOS circuits. The CMOS inverter represents a low-power alternative to the depletion load inverter circuit. FIG. 1 represents schematically a typical CMOS inverter 20. The inverter 20 includes both a p-channel enhancement transistor 22 and an n-channel enhancement transistor 24. As shown, the inverter 20 is generally symmetric with respect to the inverter input terminal 26 and output terminal 28. The gates 30 and 32 of the p-channel transistor 22 and n-channel transistor 24, respectively, are connected together and serve as the input terminal 26. An input voltage V.sub.in is coupled to the input terminal 26 relative to ground.
The drain regions 34 and 36 of the p-channel transistor 22 and n-channel transistor 24, respectively, are connected together and serve as the output terminal 28. An output voltage V.sub.out is presented at the output terminal 28 with respect to ground. The source region 38 of the p-channel transistor 22 is connected to a positive voltage V.sub.DD. On the other hand, a more negative voltage V.sub.SS or ground is connected to the source region 40 of the n-channel transistor 24. A typical logic symbol representing the inverter 20 is illustrated in FIG. 2.
As is well known, when a logic "1" signal (e.g., 5 volts) is input to the input terminal 26, the inverter 20 will output a logic "0" signal (e.g., 0 volts) at the output terminal 28. Conversely, if a logic "0" is input the inverter 20 will output a logic "1".
In CMOS, as with most other technologies, the trend is to design circuits capable of operating at higher speeds. In addition, the trend is to design circuits with reduced line widths so as to increase the density/reduce the size thereof. As CMOS inverters are designed to operate at higher speeds and with reduced line widths, the gate RC delay of the inverter begins to play a larger role with respect to the performance of the inverter as well as any associated circuitry. The gate RC delay relates generally to the resistance of the gates of the respective p-channel and n-channel transistors making up the inverter. In addition, there exists intrinsic gate capacitance of the transistors which combines with the gate resistance to result in the gate RC delay.
Previously, the gate resistance and capacitance induced propagation delay for a CMOS inverter (herein referred to as the "gate RC delay") has been difficult to determine analytically. Many design applications such as the commonly known and commercially available SPICE simulation software rely on a mature model of the device requiring a large number of design parameters. Such a mature model of an inverter typically is not available during the early stages of circuit development. This makes it more difficult for designers to design and fabricate a complete CMOS circuit incorporating one or more inverters which will perform satisfactorily at a particular operating frequency and/or design width.
In view of the aforementioned shortcomings associated with previous approaches to designing and manufacturing CMOS inverters, there is a strong need in the art for a system which estimates a gate RC delay or related parameter as a function of technical parameters readily available in the early stages of design. For example, there is a need for a system which estimates a gate RC delay of a CMOS inverter without requiring a mature model. Similarly, there is a strong need for a system which determines a width of the n-channel and p-channel transistors in order to achieve a given gate RC delay.